In virtually all communication systems, data is transferred from a transmitting node of the communication system to a receiving node over a communication path. Such a path may be a wired or wireless connection between the communicating nodes. In many of these systems, the data take the form of a digital signal transferred at a substantially constant rate over the connection. Normally, the data signal presents a series of binary digits (“bits”) that represent the digital information being transmitted to form a serial communication path. Further, several such series of bits transferred simultaneously may form a multi-path, parallel communication connection.
Some communication systems also supply a data clock signal over the same connection to provide timing information for the data signal. Typically, the data signal is sampled, or “clocked,” at each logic “low” to logic “high” transition of the data clock to identify each bit being transferred. However, other communication systems do not provide a clock signal along with the data signal over the connection, instead relying on the receiving node's knowledge of the transfer rate of the data signal to allow proper interpretation of the data signal.
Unfortunately, drift of the data signal frequency, variations in the frequency of a local oscillator from which the data clock is derived, and similar problems may cause the receiving node to improperly clock the data signal. To counteract such problems, the receiving node is often equipped with a data clock recovery system to help ensure proper sampling of the data signal.
One example of such a system 100 is shown in FIG. 1. A data sampler 102 samples an input data stream 110 received over a communication system connection by way of a data clock 112, resulting in a sampled input data stream 114 for use by the receiving node. The data sampler 102 also compares the phase of the input data stream 110 with the data clock 112 by sampling near the logic transitions of the input data stream 114 by way of an edge clock 113, in addition to the sampled input data stream 114. Based on the values of the input data stream 110 as sampled by the data clock 112 and the edge clock 113, the data sampler 102 generates a phase difference signal 118 indicating if the transitions of the data clock 112 are being generated early (“leading”) or late (“lagging”) compared to a preferred phase. Typically, the preferred phase of the data clock 112 results in sampling the input data stream 110 at substantially the midpoint between the transitions of the input data stream 110 to help avoid sampling while the input data stream 110 is transitioning between logic states. Thus, the edge clock 113 is essentially 180 degrees out of phase with the data clock 112. FIG. 2 illustrates the relative phase relationship between the input data stream 110, the data clock 112, and the edge clock 113 under ideal conditions.
More specifically, if a value of the input data stream 110 is the same at a rising edge of the edge clock 113 and the next rising edge of the data clock 112, the phase difference signal 118 may indicate the data clock 112 lags its preferred phase. Conversely, if the values of the input data stream 110 at the rising edge of the edge clock 113 and the next rising edge of the data clock 112 are different, the phase difference signal 118 may indicate the data clock 112 leads its preferred phase.
In the particular implementation of FIG. 1, the data clock 112 and the edge clock 113 are derived from a multiphase local clock 116 originating in the receiving node. These phases are shown in the timing diagram of FIG. 3 as CP0-CP3, thus indicating that the multiphase clock 116 provides four phases spaced 90 degrees apart. In addition, other phases of the local clock 116 (indicated as CI01-CI03, CI11-CI13, CI21-CI23, and CI31-CI33) are generated by way of a phase interpolator 108 driven by the local clock 116. In the particular example of FIG. 2, sixteen total phases are supplied by the phase interpolator 108, which employs one of these phases as the data clock 112 to produce the sampled data input stream 114, and another approximately 180 degrees out of phase with the data clock 112 as the edge clock 113.
A counter 104 takes the phase difference signal 118 as input to produce a phase count 120, which accumulates the phase indications provided by the phase difference signal 118. More specifically, for each bit period in which the data clock 112 lags its preferred phase, the counter 104 increments the phase count 120 by one. Conversely, for each bit period in which the data clock 112 leads the preferred phase, the counter 104 decrements the phase count 120 by one.
In further reference to FIG. 1, a threshold comparator 106 compares the phase count 120 with a threshold value. The threshold value is typically utilized to prevent unnecessary adjustments in the phase of the data clock 112 in reaction to noise or temporary phase misalignment between the data clock 112 and the input data stream 110. If the phase count 120 exceeds the threshold, or falls below the negative of the threshold, the threshold comparator 106 produces a pulse on a phase shift signal 122 to either advance or delay the phase of the data clock 112 and the edge clock 113 simultaneously, depending on the sign of the phase count 120. Once the pulse on the phase shift sign 122 is generated, the counter 104 resets the phase count 120 to zero. In one example, the phase shift signal 122 includes two separate signal lines, with one line providing pulses to delay the phase of the data clock 112 and the edge clock 113 by a portion of a period, and another line supplying pulses to advance the phase of the data clock 112 and the edge clock 113 by a portion of a period.
The phase shift signal 122 is accepted as input by the phase interpolator 108, described above, to drive the data clock 112 and the edge clock 113 with the appropriate phases of the local clock 116 or any of its interpolated phases, as depicted in FIG. 3. For example, if the data clock 112 is currently derived from interpolated clock phase C122, the edge clock 113 would be derived from the interpolated clock phase C102, which is 180 degrees out of phase with the interpolated clock phase CI22. If the phase shift signal 122 then indicates that the phase of the data clock 112 utilized to produce the sampled input data stream 114 should be delayed, the phase interpolator 108 begins deriving the data clock 112 from interpolated clock phase C123, and the edge clock 113 from interpolated clock phase C103. Adjusting the phase in this manner allows the rising transitions of the data clock 112 to more closely align with the midpoint of each bit period of the input data stream 110.
FIG. 4 presents an idealized timing diagram of a common scenario in which the frequency of the input data stream 110 and the data clock 112 are closely matched. The preferred phase of the data clock 112 in this example is shown by way of vertical dotted lines in FIG. 4. Also, a threshold of 64 is presumed in this particular example. In addition, the logic state of the input data stream 110 is presumed to change every bit period to provide phase information concerning the data clock 112 and the edge clock 113 for every period of the data clock 112.
Presuming the data clock 112 slightly lags its preferred phase, the phase difference signal 118 generated by the data sampler 102 indicates this state during each period of the data clock 112. As a result, the counter 104 increments the phase count 120 each data clock 112 period in which it lags its preferred phase. Once the phase count 120 reaches the threshold value of 64, the threshold comparator 106 indicates by way of the phase shift signal 122 for the phase interpolator 108 to slightly advance the phase of the data clock 112 and the edge clock 113, typically by way of an advance pulse 150. Also, the counter 104 resets the phase count 120.
Once the phase interpolator advances the phase of the data clock 112 and the edge clock 113 by way of the local clock 116, the data clock 112 leads its preferred phase for several data clock 112 cycles, as indicated by the phase difference signal 118 from the data sampler 102. As a result, the counter 104 causes the phase count 120 to decrement for several data clock 112 cycles, thus being reduced in value from 0 to −64, causing the threshold comparator 106 to indicate via a delay pulse 152 of the phase shift signal 122 to the phase interpolator 108 to delay the phase of the data clock 112 and the edge clock 113. Once this phase shift has been accomplished, the phase count 120 is reset, and the data clock 112 lags its preferred phase, causing the cycle to begin anew.
Thus, the data clock recovery circuit 100 may induce a somewhat periodic phase shifting of the data clock 112 when in fact the frequencies of the input data stream 110 and the data clock 112 are nearly identical. Such unnecessary phase shifting of the data clock 112 results in “phase jitter” between the data clock 112 and the input data stream 110, which typically induces reduced link performance and limited data transfer rates, due the resulting phase instability of the data clock 112.